1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to using a selective deposition to form sidewall spacers in a self-aligned manner laterally adjacent to opposed sidewall surfaces of a transistor gate conductor.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline ("polysilicon") material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
Operating transistors which have heavily doped source/drain regions arranged directly adjacent the gate conductor often experience a problem known as hot carrier injection ("HCI"). HCI is a phenomena by which the kinetic energy of the charged carriers (holes or electrons) is increased as they are accelerated through large potential gradients, causing the charged carriers to become injected into and trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. As a result of carrier entrapment within the gate oxide, a net negative charge density forms in the gate oxide. The trapped charge can accumulate with time, resulting in a positive threshold shift in a NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome problems of sub-threshold current and threshold shift resulting from HCI, an alternative drain structure known as the lightly doped drain ("LDD") is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce Em. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section within the active area (hereinafter "junction") at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. The second implant dose forms a heavily doped source/drain region within the junction laterally outside the LDD area. In this manner, the lateral thickness of the sidewall spacers dictates the length of the LDD areas.
Unfortunately, the addition of LDD areas adjacent the channel adds parasitic resistance to the source/drain pathway, leading to many deleterious effects. For example, the parasitic resistance causes an increase in the value of the gate-to-source voltage, V.sub.GS, required for the drive current, I.sub.D, (i.e., current flowing between the source and drain regions of the transistor) to reach saturation. Reducing the parasitic resistances associated with the source and drain regions would help inhibit these deleterious effects; however, decreasing the drain parasitic resistance, R.sub.D, is not viable since HCI prevention is necessary. Thus, the source-side and drain-side LDD lengths must be properly controlled to ensure that source-side parasitic resistance, R.sub.S, is minimized while at the same time attenuating Em at the drain-side of the channel. If the lateral thickness of the drain-side sidewall spacer is too small, then the corresponding LDD length might not sufficiently suppress HCI. Yet, if the source-side spacer is too large, then R.sub.S may unduly jeopardize transistor operation. It may thus be desirable to form a transistor such that the source-side LDD length is smaller than the drain-side LDD length.
In order to form LDD areas of varying lengths for a transistor, several steps must be employed. First, an LDD implant self-aligned to the sidewall surfaces of a gate conductor is forwarded into a semiconductor substrate. A first spacer material is deposited across the substrate and the gate conductor. The first spacer material is anisotropically etched to form a first spacer layer upon each of the sidewall surfaces of the gate conductor. A masking layer is then formed across one of the first spacer layers and the LDD area adjacent that first spacer layer. A source/drain implant self-aligned to the exposed lateral edge of the unmasked first spacer layer is forwarded into exposed regions of the substrate. The masking layer is removed, and a second spacer material is deposited and etched to form a second spacer layer upon the first spacer layer. Another source/drain implant self-aligned to the exposed lateral edge of the second spacer layer is forwarded into the substrate. The resulting transistor includes one LDD area, preferably the source-side LDD area, having a length approximately equal to the lateral thickness of the first spacer layer. It also includes another LDD area, preferably the drain-side LDD area, having a length approximately equal to the combined lateral thicknesses of the first and second spacer layers. Alternately, an asymmetrical transistor may be formed having only a drain-side LDD area by aligning the source implant to a sidewall surface of the gate conductor and aligning the drain implant to the lateral edge of a sidewall spacer formed as described above.
A transistor employing sidewall spacers formed using a conventional technique is depicted in FIG. 1. A gate conductor 24 is spaced above a semiconductor substrate 20 by a gate oxide 22. Oxide sidewall spacers 28 are arranged upon the opposed sidewall spacers of gate conductor 24. LDD areas 26 are disposed within substrate 20 directly underneath sidewall spacers 28. Source/drain regions 30 are arranged within substrate 20 laterally adjacent LDD areas 26. The peak of each of the oxide sidewall spacers 28 is shown as being positioned at a level below the upper surface of gate conductor 24. This positioning of the sidewall spacer peak may occur as a result of using anisotropic etching to define oxide spacers 26. Ion bombardment during anisotropic etching occurs more frequently upon vertical surfaces than horizontal surfaces of the material being removed. Thus, during the formation of oxide sidewall spacers 28, after oxide upon the upper surface of gate conductor 24 has been completely removed, a lateral thickness of oxide remains upon the sidewall surfaces of the gate conductor. If this lateral thickness of oxide is greater than that of the desired lateral thickness of sidewall spacers 28, the anisotropic etch duration is typically extended until the desired spacer thickness is reached. The type of anisotropic etch employed may exhibit a high selectivity to oxide, thereby preventing removal of substrate 20 and gate conductor 24 which comprise silicon. Unfortunately, a substantial portion of the upper portion of sidewall spacers 28 may be removed, resulting in the arrangement of the oxide spacers depicted in FIG. 1.
Integrated circuit formation involves electrical linkage of various active devices, i.e., transistors. Contacts are formed through an interlevel dielectric to the electrically active areas, and multiple levels of dielectrically isolated interconnect are routed to the contacts. Formation of a contact coupled to the gate conductor involves etching an opening vertically through an interlevel dielectric down to the gate conductor using a conventional optical lithography technique and an etch technique highly selective to the interlevel dielectric material. Unfortunately, misalignment of the photoresist masking layer may occur during optical lithography, causing the contact opening to form such that it extends down to the peak of one of the oxide sidewall spacers. Further, this misalignment of the masking layer may permit ion bombardment of that oxide sidewall spacer during the, e.g., etch of an oxide-based interlevel dielectric. As a result, the contact opening may extend well below the surface of the gate conductor. Thus, when a conductive material, such as tungsten is deposited into the contact opening, it may become arranged laterally adjacent to the gate conductor in regions where the sidewall spacer has been removed. This configuration of the conductive material may provide for unwanted capacitive coupling or electrical linkage between the gate conductor and the source/drain regions.
It would therefore be desirable to devise a method for forming a sidewall spacer to a desired lateral thickness without the peak of the spacer being removed to a level below the surface of the adjacent gate conductor. The sidewall spacer must effectively prevent electrical shorting between the gate conductor and adjacent junction. Thus, it would also be beneficial to form sidewall spacers which are substantially resistant to attack by etchants which are highly selective to oxide. Further, it would be desirable to develop a technique for efficiently forming a transistor having different source-side and drain-side LDD lengths using substantially fewer steps. Since the lateral thicknesses of the sidewall spacers employed by a transistor determines the LDD lengths, effectively controlling spacer thickness is important.